1. Field of the Invention
The present invention relates to a digital PLL (referred to hereinbelow as DPLL) circuit, and more particularly to a DPLL circuit in a synchronization circuit unit for generating a reference clock source to be used in transmission devices (optical transmission devices, mobile communication devices, and the like) located in digital synchronization networks.
2. Description of the Related Art
Clock sources serving as a reference are the most significant components of digital synchronization networks, and cesium atomic oscillators as primary standard are generally used therein. Transmission devices in a synchronization network comprise a synchronization circuit unit for generating clock signals to be used in the devices based on the clocks distributed from the reference clock source.
Characteristics of clock signals generated by the synchronization circuit units are specified in detail for each subordinate hierarchical level (stratum) in the synchronization network by ITU810, GR-1244 (Bellcore). A state in which autonomous operation is initiated by a frequency drift immediately prior to fault generation at the time of reference clock fault generation and the operation is conducted at an accuracy of a slave oscillator is called “holdover” and frequency accuracy during such holdover is also specified as one of those characteristics.
Here, a DPLL (Digital Phase Lock Loop) circuit used for synchronizing a clock signal used in the device with the inputted reference clock signal in the synchronization circuit unit will be explained below in a simple manner.
FIG. 1 is a block diagram illustrating a general configuration example of a DPLL circuit. Referring to FIG. 1, a section 100 surrounded by a solid line is the DPLL circuit. A synchronization network clock signal from a digital synchronization network is divided by N with a 1/N divider 102 and inputted as a reference clock signal (REF_CLK).
In the DPLL circuit 100, a digital phase comparator (DPD) 1 outputs a count value corresponding to the phase difference between the reference clock signal (REF_CLK) and a feedback clock (FB_CLK).
FIG. 2 illustrates the comparison operation of the digital phase comparator (DPD) 1. In FIG. 2, (A) is the reference clock signal (REF_CLK) and (B) is the feedback signal (FB_CLK). A clock signal from an internal high-accuracy oscillator 2 is inputted into the digital phase comparator (DPD) 1 via an analog PLL circuit 3.
The digital phase comparator (DPD) 1 comprises a counter and initiates the counter of output clocks of the analog PLL circuit 3 at the rising edge of the reference clock signal (REF_CLK) (A). Then, the count of the counter is terminated at the falling edge of the feedback signal (FB_CLK) (B). As a result, the digital phase comparator (DPD) 1 counts the number of output clocks of the analog PLL circuit 3 in the period corresponding to a phase difference between the reference clock signal (REF_CLK) and feedback signal (FB_CLK) and outputs the counter count value corresponding to this phase difference.
Returning to FIG. 1, the counter clock value corresponding to the phase difference from the digital phase comparator (DPD) 1 is inputted as a phase error signal into the digital loop filter (DLF) 4. The digital loop filter (DLF) 4 integrates the counter count value and averages the inputted phase error signal.
Then, the error average value obtained in the digital loop filter (DLF) 4 is converted into an analog signal by the D/A converter 5 and inputted into a voltage control oscillator (VCO) 6 which is a slave oscillator. Therefore, the voltage control oscillator 6 outputs the signal of the frequency corresponding to the input analog voltage as an internal clock of a transmission device. At the same time, a frequency of the frequency signal is divided into 1/N by the 1/N divider 7 and feedback returned as a feedback signal (FB_CLK) to the digital phase comparator (DPD) 1. Therefore, the oscillation frequency of the slave oscillator is controlled so as to be synchronized with the reference clock (REF_CLK).
FIG. 3 relates to the case where a direct digital synthesizer (DDS) is used for a slave oscillator. Components identical to those shown in FIG. 1 are assigned with the same reference numerals.
The direct digital synthesizer (DDS) 8 is a circuit for synthesizing, by means of digital data, and creating an oscillation waveform to be outputted by employing a clock generated by a fixed oscillator 2 with a high internal accuracy as a source. In the example shown in FIG. 3, the output from the digital filter 4 is equivalent to the digital data.
In a DPLL circuit 100 shown in FIG. 1 and FIG. 3, the set resolution of the output frequency depends on the bit width of the D/A converter 5 or direct digital synthesizer 8 and shows discrete changes with respect to time T, as shown in FIG. 4, but as an average frequency drift, it assumes a value close to ±0.
However, within the framework of the conventional technology illustrated by FIG. 1 and FIG. 3, the control voltage (digital data when the direct digital synthesizer (DDS) 8 shown in FIG. 3 is used) of the slave oscillator during the holdover assumes a fixed value. This fixed value is determined based on the information at the time of reference clock synchronization.
This determination can be conducted in a simple manner by a method employing a voltage (data) immediately preceding the generation of fault in the reference signal or a method by which the feedback data during synchronization are accumulated in a buffer, and when a fault is detected, the average value of the accumulated data is computed.
The invention described in Japanese Patent Application Laid-open No. 2002-353807 is known as an example of the conventional technology. This invention was created to resolve the following problem: when the reference clock was degraded, the voltage value of the voltage control oscillator was reset to the value during synchronization, the holdover state was not assumed and the synchronization clock matched the fluctuating reference signal. With this invention, the control voltage value for control in synchronization with the reference clock is written into a memory and the range of the control voltage corresponding to the preset frequency control range is corrected based on the control voltage value.